1. Technical Field
The present invention relates to a semiconductor device and a method of manufacturing the same.
2. Related Art
Semiconductor devices are fabricated through a process of implanting impurities into a region in a silicon wafer or depositing a material on the silicon wafer, or the like. Semiconductor devices include many elements such as transistors, capacitors, or resistors to perform fixed purposes and these elements are connected to each other to receive or transmit data or signals.
As fabrication technology of semiconductor devices advances, efforts to form as many chips as possible on one wafer have continued by improving the integrity of semiconductor devices. Thereby, a minimum line width on a design rule becomes smaller to increase integrity. Further, in the semiconductor devices, high speed operation and low power consumption are required.
In order to improve the integrity of a semiconductor device, dimensions of components within the semiconductor device have to be scaled down and lengths and widths of interconnections have to be reduced. For example, typically a word line for transferring a control signal and a bit line for transferring data are the interconnections used within a semiconductor memory device. When widths or cross-sectional sizes of the word line and the bit line are reduced, resistance, which interrupts the transmission of the control signal or data, is increased. Such resistance delays the transmission speed of signals or data within the semiconductor device, increases power consumption, and further damages operation stability of the semiconductor memory device.
On the other hand, when the widths of the word line and bit line are maintained, as in the related art, to prevent an increase in resistance regardless of increases in the integrity, the physical distance between adjacent word lines or bit lines decreases. As compared with the word line to which a control signal having a relatively high potential is transmitted, the bit line that transfers data from the unit cell capacitor may not normally transfer the data due to parasitic capacitance. When the data is not smoothly transferred through the bit line, the sense amplifier, which senses and amplifies the data, may not sense the data and thus the semiconductor device cannot output data stored in the unit cell.
There is a method of increasing amounts of charges corresponding to data output from the unit cell in order to solve the problems due to the increase of parasitic capacitance in the bit line, but the size of a capacitor within a unit cell of a semiconductor memory device has to be increased to obtain this result. However, as the integrity of the semiconductor memory device increases, an area occupied by the capacitor within the semiconductor memory device shrinks.
Shrinkage of the area occupied by the capacitor occurs when the size of a unit cell of a semiconductor device is reduced. For example, a unit cell may be reduced from 8F2 to 6F2 or from 6F2 to 4F2. Here, “F” denotes a minimum pattern size obtainable under a given design rule. The smaller a unit cell size, the shorter the distance between the fine patterns.
6F2 denotes that the size of the unit cell is reduced by 2F2 as compared with a semiconductor device under an 8F2 configuration. Thus, in the semiconductor device with the size of the unit cell of 8F2, an active region has an elliptical shape in which a longitudinal axis is parallel to a longitudinal axis of a bit line, and a word line has a protruding structure on a semiconductor substrate. On the other hand, in the semiconductor device with the size of the unit cell of 6F2, an active region has an elliptical shape in which a longitudinal axis thereof is inclined to a predetermined angle with respect to a longitudinal axis of a bit line, and a word line has a buried gate structure buried within a semiconductor substrate.
In a semiconductor device with the size of the unit cell of 6F2, a bit line contact plug is in contact with the active region between the buried gates and the bit line is stacked on the bit line contact plug to be in contact with an upper portion of the bit line contact plug. In addition, a storage node contact plug is disposed at both sides of the bit line to be in contact with the active region. However, when the bit line is misaligned so that the bit line is not in contact with a central portion of the bit line contact plug, but is in contact with an edge of the bit line contact plug, the bit line contact plug is in contact with the storage contact plugs disposed at both sides of the bit line, thereby resulting in an electrical short. On the other hand, when the bit line is formed to have a large width or a bit line sidewall spacer is formed to have a thick width, a contact area between the active region and the storage node contact plug is reduced, thereby increasing resistance.